Objective. Students will write equivalent control logic in function block diagram (FBD) and structured text (ST) to demonstrate that IEC 61131-3 languages produce the same result, and will identify which language is most appropriate for given control tasks.
This lesson, its worked examples and its practice questions has not yet been verified by a licensed engineer or certified journey-level tradesperson or by a certification or approval body. It is a study draft and may contain errors. Do not use it as instructions for work on a job site or on live equipment. Always follow your instructor, your supervising professional, and current official references and regulations.
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IEC 61131-3 is the international standard that defines five PLC programming languages. Because all five languages operate on the same underlying data and produce the same control results, you can choose the language that best fits the task at hand. This lesson focuses on two of those languages: Function Block Diagram (FBD) and Structured Text (ST).
FBD is a graphical language that looks like an electrical schematic turned into a signal-flow diagram. Logic is built by placing function blocks on a canvas and connecting their inputs and outputs with lines called connections. Data flows from left to right: the output pin of one block feeds the input pin of the next.
Common standard function blocks include:
FBD is especially well suited to data-flow problems — analog signal conditioning, PID loop configuration, and motor interlock logic — because the connections make signal paths easy to trace. Engineers who work with block diagrams in instrumentation or process control often find FBD the most intuitive language.
In Lesson 4 you built a seal-in (latching) motor-start circuit in ladder diagram. The same logic in FBD uses a single SR block:
The result is identical hardware behavior: pressing START latches the motor ON; pressing STOP unlatches it. FBD makes the latch relationship visible without drawing rungs.
Structured Text is a text-based, high-level language that resembles Pascal or C. Logic is written as statements that the PLC executes line by line within each scan. Key syntax elements include:
A simple ST snippet for the Lesson 5 counter-reject sequence might look like this:
```
IF PartSensor AND NOT Reject_Active THEN
PartCount := PartCount + 1;
END_IF;
IF PartCount >= RejectThreshold THEN
Reject_Active := TRUE;
PartCount := 0;
ELSIF RejectTimer.Q THEN
Reject_Active := FALSE;
END_IF;
```
ST is especially strong for mathematical calculations, scaling, PID algorithms, complex branching logic, and sequential batch recipes where the step-by-step logic reads more clearly as text than as a ladder or diagram.
| Control Task | Best-Fit Language | Reason |
|---|---|---|
| Motor interlock, relay replacement | Ladder Diagram (LD) | Familiar to electricians; matches relay logic |
| Signal flow, PID, analog processing | FBD | Visual data-flow matches process diagrams |
| Math-heavy, batch recipes, complex branching | Structured Text (ST) | Clean syntax for calculations and conditions |
| Step-by-step process sequences | Sequential Function Chart (SFC) | Steps and transitions map directly to process phases |
| Specialized, legacy bit-manipulation | Instruction List (IL) | Low-level, rarely used in new designs |
Most modern platforms (TIA Portal, Studio 5000) allow you to mix languages in the same project, assigning each program object the language that suits it best.
Before connecting to or modifying a running PLC trainer:
1. Lockout/Tagout (LOTO) per OSHA 29 CFR 1910.147: de-energize the trainer, apply a personal lock, and verify zero energy before any wiring changes.
2. Machine guarding (OSHA 1910.212): confirm all guards are in place before enabling outputs.
3. NFPA 70E: verify absence of voltage with a properly rated meter before touching any terminal. Wear appropriate PPE for the voltage level present.
4. During software download, warn anyone near the trainer that outputs may energize. Never reach into a machine while downloading.
5. Test new programs at reduced speed or with outputs disabled until logic is confirmed correct.
Answer each question, then check it. Nothing is recorded; this is your own practice.
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